Frequency synthesizers have a wide range of applications, including wide-band communication systems and information-processing systems. As the speed and power requirements of these applications become more demanding, it is increasingly important that frequency synthesizers are capable of a fast locking time. Locking time is an important performance metric of a frequency synthesizer, because a long locking time means longer start-up times and greater start-up power consumption. The locking time of a frequency synthesizer is essentially the amount of time that it takes, after the loop of the frequency synthesizer has been enabled, for the local oscillator signal to settle to within a certain percentage of the steady-state frequency. Prior-art frequency synthesizers generally start operation by closing the loop at a random moment. As a result, the locking time of prior-art frequency synthesizers varies randomly and can be at times relatively long. The duration of the locking time also depends on parameters of many of the elements of the frequency synthesizer, including the frequency of the reference-clock signal, the current of the charge pump, the gain of the voltage-controlled oscillator, the order of the loop filter, the bandwidth of the loop and the frequency-divide ratio of the frequency divider. Prior art efforts at minimizing locking time have primarily focused on optimizing these parameters. A need remains for improved techniques for minimizing the locking time of frequency synthesizers.